Reed Solomon Forward Error Correction Encoder Decoder
The core enables quick and reliable deployment of both the encoder and the decoder. The symbol size (m) is application specific usually 8 or 10 bits and the error correction capability depends on the parity bits attached to the message (n-k)/2 = t.
The IP can be accommodated to any parameter set available and has gone through extensive testing. The IP core is silicon proven, heavily tested in UVM regression environment and has been the key component for all of the IP cores in our portfolio which use RS-FEC encoding.
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