MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, N7, N5A)
Reed Solomon Error Correcting Code ECC
Zero latency, low gate count, low power, asynchronous Reed Solomon Code based Error correction FEC:
The whole operation of encoding and decoding is asynchronous and is pure combinatorial gates without use of any synchronous logic, making it zero latency RTL.
Symbol size is ‘m’ bits for all Galois Field operations.
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