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Reed Solomon Encoder IP Core
A high performance, fully configurable Reed Solomon Encoder IP Core that is intended for use in a wide range of applications requiring forward error correction.
特色
- Supports different Reed-Solomon coding standards
- Code rate can be dynamically varied
- Parameterizable bits per symbol (M)
- Programmable codeword length (NVAL) with parameterizable maximum value (N)
- Programmable number of errors (TVAL) with parameterizable maximum value (T)
- Shortened codes supported (NVAL,TVAL)
- User configured primitive field polynomial
- User configured generator polynomial
- Synchronous design
- Low latency - 2 cycles
- Single symbol rate clock
优势
- Flexible
- Compact
- Cost-effective
可交付内容
- Verilog Source Code
- Test Bench
- Sample Syntheis scripts
- Dcumentation
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