MIPI D-PHY Rx-Only 2 Lanes in TSMC (40nm, 28nm, 22nm, 16nm, 12nm, N7, N6)
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Real Time Video Image rotation HD up to 1920x1080p60Hz
The IV-ROT IP implements a full rotation (0-360°) algorithm for high resolution images like HD (1920x1080p30/ 1920x1080p60). The maximum resolution is 2048x2048.
The throughput of the design is 1 pixel per cycle on 3 components 8bit each (e.g. RGB or YUV444). The rotation process requires about 1 frame delay through external SDRAM/DDR. The picture content can be interlaced or progressive. De-interlacing is recommended (iv-deint)
Programmable parameters are:
- pictures size xy
- rotation base xy
- rotation angle Δω
- rotation size xy
Program parameters changes are applied during vertical blanking. The algorithm requires about 3 full frame storage. Rotation starts when one full picture is written to memory. Processed pixel are directly displayed.
The throughput of the design is 1 pixel per cycle on 3 components 8bit each (e.g. RGB or YUV444). The rotation process requires about 1 frame delay through external SDRAM/DDR. The picture content can be interlaced or progressive. De-interlacing is recommended (iv-deint)
Programmable parameters are:
- pictures size xy
- rotation base xy
- rotation angle Δω
- rotation size xy
Program parameters changes are applied during vertical blanking. The algorithm requires about 3 full frame storage. Rotation starts when one full picture is written to memory. Processed pixel are directly displayed.
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