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Quad SPI Master IP
QUAD SPI MASTER is full-featured, easy-to-use, synthesizable design, compatible with standard protocol of SPI Vendor Specifications.Through its QUAD SPI compatibility,it provides a simple interface to a wide range of low-cost devices. QUAD SPI MASTER IIP is proven in FPGA environment.The host interface of the QUAD SPI MASTER can be AMBA APB, AMBA AHB, AMBA AHB-Lite, AMBA AXI, AMBA AXI-Lite, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.
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qspi IP
- AXI QSPI with Execute in Place
- Specialized 1.2V to 3.3V Fail-Safe GPIO and 3.3V I2C Open-Drain, SPI in TSMC 110nm
- Specialized 1.2V to 3.3V Fail-Safe GPIO and 3.3V I2C Open-Drain in 110nm
- Flipchip 5V Fail-Safe GPIO, 5V GPIO, 5V GPI and I2C Compliant 5V ODIO
- Quad SPI Master IP
- QSPI FLASH Controller – XIP functionality (SINGLE, DUAL and QUAD SPI Bus Controller with Double Data Rate support)