Quad 3.125/6.25 Gbps Backplane SerDes
特色
- Backplane SerDes compliant to XAUI 3.125 Gbps and double XAUI 6.25Gb/s specifications
- High-speed differential reference clock
- Low jitter clock synthesizers for clock distribution, ASIC clock for link layer, and SSC clock for reduced EMI
- Jitter Tolerance and Jitter Generation of device exceed specifications
- 8b/10b encoder and decoder
- High speed serial drivers
- High speed serial input stage with on-chip terminations
- Auto-calibration termination
- Auto calibration Termination resistor
- Comma, Squelch, and OOB Detect for character alignment
- On-chip Near END and Far End retimed serial and parallel loopback.
- Power management modes
- Pattern generator and error checker to support BIST
- 1.0V/1.8V ±5% supply voltage
- Low power, 150 mW per channel
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