MIPI C-PHY v1.2 D-PHY v2.1 RX 2 trios/2 Lanes in TSMC (16nm,N6, N5)
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Quad 1.06/1.25/2.125/1.56/2.5/3.125 Gbps Backplane SerDes
TRC3104SBA is a Quad SerDes transceiver device, capable of transmitting 1.06 to 3.125Gb/s signals over Backplane, Fiber Channel, and cupper cables. It uses single and double data rate capability. One 1.8V supply can power the core and I/Os. It has Comma detector, low jitter clock synthesizer, 8B/10B converter, selectable pre-emphasis and equalizer, CDR PLL, BIST and loopback functions for testing, and needs only 3 external resistors for setting bias current. It is also available as core (named TRC3104CBA).
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Block Diagram of the Quad 1.06/1.25/2.125/1.56/2.5/3.125 Gbps Backplane SerDes
SerDes IP
- PCIe 5.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC
- Low-Latency SerDes PMA - 10GbE, 25GbE
- Multi-protocol SerDes PMA - PCIe1 PCIe2 PCIe3 PCIe4 PCIe5 and more
- 1-56/112G Multi-protocol Serdes (Interlaken, JESD204, CPRI, Ethernet, OIF/CEI)
- 400G ultra low latency 56/112G FEC and SERDES IP sub 10ns latency
- PCIe Gen 6 SERDES IP - supports up to 112G LR ethernet with low power and latency