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QSGMII
The Xilinx Ethernet Quad Serial Gigabit Media Independent Interface PCS/PMA or QSGMII IP LogiCORE™ IP provides an Ethernet Physical Coding Sublayer (PCS) with an aggregation of four 10/100/1000M ports to one five gigabit transceiver. QSGMII interfaces are implemented using transceivers in Virtex®-7 or Kintex™-7 devices. On the front end, the LogiCORE IP can also interface seamlessly to four Ethernet MACs through a built-in Gigabit Media Independent Interface (GMII). This IP is available through CORE Generator™ software at no charge to help you accelerate your time to market. It is built upon our existing Serial Gigabit Media Independent Interface PCS/PMA IP.
查看 QSGMII 详细介绍：
- 查看 QSGMII 完整数据手册
- 联系 QSGMII 供应商
Interface and Interconnect IP
- AXI- Interconnect : Advanced Extensible Interface Bus IP
- Universal Chiplet Interconnect Express (UCIe) Controller
- Serial Peripheral Interconnect Master & Slave Interface Controller
- UCIe/BoW BlueLynx™ Dual Mode PHY and subsystem IP for chiplet interconnect
- Physical Layer Interface Core
- PCIe 5.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC