PSRAM PHY

The INNOSILICON DDR IPTM Mixed-Signal PSRAM PHY provides turnkey physical interface solutions for ICs requiring access to JEDEC compatible PSRAM devices. It is optimized for low power and high speed applications with robust timing and small silicon area. It supports APmemory UHS PSRAM components in the market. The PHY components contain PSRAM specialized functional and utility 2.5V IO devices, critical timing synchronization module (TSM), the low-jitter PLL, the TX and RX logic control for the PSRAM interface.
Note that all INNOSILICON PHY is pre-assembled with.lib, LEF and GDS so that it is very easy to integrate the PHY with any existing SoC floor plan. The DQ bus width can support 8 bit to match the PSRAM DQ interfaces. INNOSILICON is happy to pre-assemble each PHY for our customer so that integration becomes extremely easy.
The Innosilicon’s PSRAM PHY solution includes PSRAM controller and PHY. With configurable timing and driving strength parameters to interface to the wide variety of PSRAMs, the PHY is very flexible with advanced command capability to increase PSRAM operation efficiency.

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