MIPI D-PHY Universal IP - 4.5Gbps/lane, MIPI D-PHY v2.5 Compliant in TSMC 22ULP
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Programmable Peripheral Interface
The Digital Blocks DB8255A Programmable Peripheral Interface IP core is a full function equivalent to the Intel 8255A / 82C55A and Harris / Intersil 82C55A devices.
The DB8255A RTL Verilog / VHDL outputs were compared to the Intel 8255A device on a cycle-by-cycle basis as captured & represented by the Digital Blocks testbench suite.
The DB8255A implements a general-purpose I/O interface connecting peripheral equipment to a microprocessor system bus. The core generates 24 programmable I/O lines which are individually programmed in 2 groups of 12 and used in 3 major modes of operation.
The DB8255A RTL Verilog / VHDL outputs were compared to the Intel 8255A device on a cycle-by-cycle basis as captured & represented by the Digital Blocks testbench suite.
The DB8255A implements a general-purpose I/O interface connecting peripheral equipment to a microprocessor system bus. The core generates 24 programmable I/O lines which are individually programmed in 2 groups of 12 and used in 3 major modes of operation.
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