You are here:
Programmable frequency divider (56 to 16383 dividing ratio)
The cell is 14-bit programmable frequency divider. It consists of ECL prescaler with variable dividing ratio 8/9 controlled by 3-bit swallow counter and CMOS 11-bit counter. The dividing ratio is 56…16383 and current consumption weakly depends on operating frequency (50..1050 MHz).
The block is fabricated on iHP SiGe BiCMOS 0.25 um (SGB25V) technology.
The block is fabricated on iHP SiGe BiCMOS 0.25 um (SGB25V) technology.
查看 Programmable frequency divider (56 to 16383 dividing ratio) 详细介绍：
- 查看 Programmable frequency divider (56 to 16383 dividing ratio) 完整数据手册
- 联系 Programmable frequency divider (56 to 16383 dividing ratio) 供应商
frequency divider N-divider IP
- Programmable 9-bit CMOS frequency divider (2…511 dividing ratio)
- Programmable CMOS frequency divider (32...16383 dividing ratio)
- Programmable CMOS frequency divider (56..16383 dividing ratio)
- Programmable CMOS HF divider (16…4095 dividing ratio)
- 12MHz to 750MHz Integer-N Phase-Locked Loop Clock Generator
- 3GHz to 6GHz Fractional-N Phase-Locked Loop