The CMOS PLL high-frequency divider consists of the converter of a differential input signal to an unipolar signal with a supply voltage peak-to-peak, a prescaler with variable dividing ratio 8/9 and two binary decade counters.
The block is fabricated on TCMS BiCMOS 0.18 um technology.
- TCMS BiCMOS 0.18 um
- Wide range of dividing ratio (56…2047)
- Low current consumption
- Compact structure
- Wide range of operating frequency - up to 5 GHz
- Supported foundries: TSMC, UMC, Global Foundries, SMIC, iHP, AMS, Vanguard, SilTerra
- Schematic or NetList
- Abstract model (.lef and .lib files)
- Layout view (optional)
- Behavioral model (Verilog)
- Extracted view (optional)
- DRC, LVS, antenna report
- Test bench with saved configurations (optional)
- PLL frequency synthesizer