Programmable CMOS frequency divider (56..16383 dividing ratio)

The cell is 14-bit programmable frequency divider. It consists of CMOS prescaler with variable dividing ratio 8/9 controlled by 3-bit swallow counter and CMOS 11-bit counter. The dividing ratio is 56…16383 and current consumption weakly depends on operating frequency (50..1050 MHz).
The block is fabricated on iHP SiGe BiCMOS 0.25 um (SGB25V) technology.

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