You are here:
Programmable 9-bit CMOS frequency divider (2…511 dividing ratio)
The programmable CMOS frequency divider is a set of 8 serially connected dividers with the varied dividing ratio 2/3. This structure is especially effective for wide range of dividing ratio since the number of triggers to accomplish the specified ratio is minimized. The dividing ratio is 2…511.
Input frequency is 88...500 MHz.
The block is fabricated on iHP SiGe BiCMOS 0.25 um (SGB25V) technology.
Input frequency is 88...500 MHz.
The block is fabricated on iHP SiGe BiCMOS 0.25 um (SGB25V) technology.
查看 Programmable 9-bit CMOS frequency divider (2…511 dividing ratio) 详细介绍：
- 查看 Programmable 9-bit CMOS frequency divider (2…511 dividing ratio) 完整数据手册
- 联系 Programmable 9-bit CMOS frequency divider (2…511 dividing ratio) 供应商
CMOS frequency divider N-divider IP
- Programmable CMOS frequency divider (32...16383 dividing ratio)
- Programmable CMOS frequency divider (56..16383 dividing ratio)
- Programmable CMOS HF divider (16…4095 dividing ratio)
- Programmable frequency divider (56 to 16383 dividing ratio)
- Phase-locked loop clock generator
- Wide band 3Ghz-6GHz fractional phase-locked loop