The programmable 6-bit CMOS frequency divider is a set of two independent circuits. One of them is designed using 6-bit counter and is able to change input frequency dividing ratio with step 1. The second part is based on a set of serially connected dividers with the varied dividing ratio 2/3 and is able to change dividing ratio with step 0.5. Since this structure consists of the static triggers, current consumption is closed to zero when there is no input clock. The dividing ratio is 1…63. Input frequency is 10...300 MHz.
The block is fabricated on iHP SiGe BiCMOS 0.25 um (SGB25V) technology.
- iHP SGB25V
- Range of dividing ratio 1…63
- Dividing ratio change with step 0.5
- Compact structure
- Supported foundries: TSMC, UMC, Global Foundries, SMIC, iHP, AMS, Vanguard, SilTerra
- Schematic or NetList
- Abstract model (.lef and .lib files)
- Layout view (optional)
- Behavioral model (Verilog)
- Extracted view (optional)
- DRC, LVS, antenna report
- Test bench with saved configurations (optional)
- PLL frequency synthesizer