MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, N7, N5A)
Processor Development Toolset
Our approach at Codasip is to automate the development of processor cores by using a high-level description in the CodAL processor description language and generating the design implementation, verification environment, virtual system prototype, and a complete software toolchain using Codasip Studio.
In addition to its design capabilities, Codasip Studio includes powerful multiprocessor programming, debugging and profiling features, enabling the development of complex processor designs with ease.
Codasip Studio is built upon open standards and software including Eclipse, LLVM, Verilog, SystemVerilog, and UVM.
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Block Diagram of the Processor Development Toolset
Processor IP
- RT-630 Hardware Root of Trust Security Processor for Cloud/AI/ML SoC FIPS-140
- RT-660 DPA & Fault Injection Resistant Hardware Root of Trust Security Processor for Govt/Aero/Defense FIPS-140
- RT-660-FPGA DPA-Resistant Hardware Root-of-Trust Security Processor for Govt/Aero/Defense FIPS-140
- RT-630-FPGA Hardware Root of Trust Security Processor for Cloud/AI/ML SoC FIPS-140
- Secure-IC Securyzr(TM) Cyber Escort Unit IP provides real time detection of sero day attacks on processor
- 64-bit RISC-V Application Processor Core