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Power on Reset IP, Input: 1.2V, Vrr=0.8V, Vfr=0.65V, UMC 55nm LP process
Vrr=0.8V, Vfr=0.65V, input VCC=1.2V, 1.2V Power On Reset, UMC 55nm 2T LP/RVT Low-K Logic process.
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