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Power on Reset
The power on reset consists of a Schmitt trigger and simple logic for forced reset input, whish is forced asynchronous reset. Output port is setRe, that means it is low to set flip-flop in particular state.
The block is fabricated in TSMC SiGe BiCMOS 0.18 um.
The block is fabricated in TSMC SiGe BiCMOS 0.18 um.
特色
- TSMC SiGe BiCMOS 0.18 um
- Low current consumption
- Small layout area
- Supported foundries: TSMC, UMC, Global Foundries, SMIC, iHP, AMS, Vanguard, SilTerra
可交付内容
- Schematic or NetList
- Abstract model (.lef and .lib files)
- Layout view (optional)
- Behavioral model (Verilog)
- Extracted view (optional)
- GDSII
- DRC, LVS, antenna report
- Test bench with saved configurations (optional)
- Documentation
应用
- Power on reset
查看 Power on Reset 详细介绍：
- 查看 Power on Reset 完整数据手册
- 联系 Power on Reset 供应商