The S3PORTJ18D is a low-power reset circuit that provides the following feature: Power-On Reset (POR) signal that monitors the absolute value of two supplies. The logic level of this reset signal is set by the level of the power supplies and can be delayed by an internal RC oscillator and counter.
The S3PORTJ18D uses a threshold detect circuit to establish the point when it is safe for circuitry to begin functioning. This detection circuit guarantees that the supply is at a sufficient level for the circuitry to operate correctly.
The POR output signal can be delayed by varying amounts, should it be required by changing the counter division.
The S3PORTJ18D circuit is implemented in a standard 6 metal 0.18um basic logic process. It is readily portable across all foundries and process nodes upon request.
- TowerJazz 0.18μm TS18 Standard Logic Process
- Power-On Reset output
- No External Components
- Test Modes
- Deep NWell Option
- Analog Test Input Signal Port
- Characterization Report
- Flat Netlist (cdl)
- Layout View (gds2)
- Abstract View (lef)
- Timing View (lib)
- Behavioural Model (Verilog .v)
- Integration Guidelines and Support
- Deliverables are subject to Agreement
- *See product datasheet for details. Terms and conditions apply.
- Reset generation and supply monitoring for any digital or analog circuitry
Block Diagram of the Power On Reset Circuit