MIPI C-PHY v1.0 D-PHY v1.2 TX 2 trios/2 Lanes in TSMC (12nm, N5, N3P)
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Power input 3.3V, Comparator ; UMC 55nm SST uLP/HVT Low-K Logic Process
Power input 3.3V, Comparator ; UMC 55nm SST uLP/HVT Low-K Logic Process
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