Scalable, On-Die Voltage Regulation for High Current Applications
You are here:
Post Quantum Secure Boot
The TESIC-310 IP is a turnkey solution to provide a secure boot facility to an SoC. It implements the Post Quantum secure Leighton-Micali Signature (LMS) as specified in NIST SP800-208. The TESIC-310 operates as a slave peripheral to an Application Processor. It is a secure enclave that stores the keys assuring their integrity and the integrity of the firmware authentication process. The LMS signature is a robust post-Quantum secure algorithm. The parameters have been chosen to enable up to 32 thousand firmware updates with a minimal signature size of typically less than 5KBytes. The TESIC-310 is pre-certified to SESIP Level 3 and delivered as RTL. It is based on propriety IP free of 3rd party rights and royalties. The TESIC-310 operates as a slave: the Application Processor requests the validation of the firmware as part of its boot process, without having to manage any keys.
查看 Post Quantum Secure Boot 详细介绍：
- 查看 Post Quantum Secure Boot 完整数据手册
- 联系 Post Quantum Secure Boot 供应商
Secure element IP
- Securyzr iSE 100/300/700/900 neo series by Secure-IC: integrated Secure Element (iSE) for multiple applications
- Securyzr iSE S700 neo series by Secure-IC: an integrated Secure Element (iSE) for automotive
- Integrated Secure Element (iSE)
- Integrated Secure Element (iSE) for industrial IoT, factory automation, and AI devices
- TESIC CC EAL5+ Secure Element IP Core
- TESIC RISC-V CC EAL5+ Secure Element Soft/Hard Macro