TSMC 3nm (N3E) 1.2V/1.8V I3C Libraries, multiple metalstacks
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POS-PHY Level 4
The packet over SONET/SDH PHY (POS-PHY) Level 4 interface, first developed by the SATURN Development Group, was later adopted by the Optical Internetworking Forum (OIF) as the System Packet Interface Level 4?Phase 2 (SPI-4.2). Therefore, POS-PHY Level 4 and SPI-4.2 are synonymous.
The POS-PHY Level 4 MegaCore function uses the SPI-4.2 interface for high-speed cell and packet transfers between PHY and link-layer devices. The SPI-4.2 interface supports a data width of 16 bits (LVDS solution), and can be a PHY-link, link-link, link-PHY, or PHY-PHY connection in multi-gigabit applications, including ATM and POS (STS-192/STM-64), 10 Gigabit Ethernet, and multi-channel gigabit and fast Ethernet.
The POS-PHY Level 4 MegaCore function uses the SPI-4.2 interface for high-speed cell and packet transfers between PHY and link-layer devices. The SPI-4.2 interface supports a data width of 16 bits (LVDS solution), and can be a PHY-link, link-link, link-PHY, or PHY-PHY connection in multi-gigabit applications, including ATM and POS (STS-192/STM-64), 10 Gigabit Ethernet, and multi-channel gigabit and fast Ethernet.
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Communication IP
- Software Defined Radio for High Throughput PTP and PTMP network communication
- NFC Tag IP for Proximity Integrated Circuit Cards (PICC) and Vicinity Integrated Circuit Cards (VICC) Active/Passive
- Enhanced Multiprotocol Serial Communication Controller
- Serial Communication Controller
- Interlaken Communication Controller
- Run Time Phase Alignment Circuit