POS-PHY Level 4
The POS-PHY Level 4 MegaCore function uses the SPI-4.2 interface for high-speed cell and packet transfers between PHY and link-layer devices. The SPI-4.2 interface supports a data width of 16 bits (LVDS solution), and can be a PHY-link, link-link, link-PHY, or PHY-PHY connection in multi-gigabit applications, including ATM and POS (STS-192/STM-64), 10 Gigabit Ethernet, and multi-channel gigabit and fast Ethernet.
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Communication IP
- Software Defined Radio for High Throughput PTP and PTMP network communication
- Enhanced Multiprotocol Serial Communication Controller
- Multifunctional DSP Architecture for High-Performance, Low-Power Audio/Voice/Sensing and Wireless Communication Applications
- Highly powerful, multi-mode communication processor for IoT wireless applications
- Serial Communication Controller
- Interlaken Communication Controller