The eSi-AHB-POLY1305 core is an easy to use POLY1305 accelerator peripheral that is fully compliant with the RFC7539 IETF standard.
Poly1305, along with the CHACHA20 encryption algorithm, has been specified for use in the TLS protocol, within RFC7905.
- Processing of a 128-bit dataword in as low as 4 clock cycles
- Different processing architectures offering different balances between throughput/area
- Fixed time processing for resistance against timing attacks
- Simple register-based interface
- Split clock domains allow power reduction by using the AHB clock domain for configuration, with a local system-clock domain to perform processing
- AMBA 3 AHB slave interface for configuration
- Optional support for interfacing with DMA-engine for greater throughput
- Verilog 2001
- Easy integration into Arm or other microprocessor SoC
- Small size and high performance
- Software libraries
- Transport Layer Security (TLS)
- Ultra-low power embedded web-servers
Block Diagram of the Poly1305 core with AHB interface