You are here:
PLL (Spread Spectrum) IP, UMC 40nm LP process
Input clock range:5 ~ 1280MHz, output clock range:15.625 ~ 2000MHz wide-range SSCG, UMC UMC 40nm LP/LVT Low-K Logic process.
查看 PLL (Spread Spectrum) IP, UMC 40nm LP process 详细介绍：
- 查看 PLL (Spread Spectrum) IP, UMC 40nm LP process 完整数据手册
- 联系 PLL (Spread Spectrum) IP, UMC 40nm LP process 供应商
Clock IP IP
- TSMC CLN7FF 7nm Clock Generator PLL - 800MHz-4000MHz
- TSMC Samsung GF Intel CML mux - on-chip clock buffer
- TSMC FPD-Link / OpenLDI / LVDS forwarded clock SERDES Link
- Adaptive Clock Generation Module for DVFS and Droop Response
- TSMC CLN20SOC 20nm Clock Generator PLL - 700MHz-3500MHz
- MEMS-based Clock Generator with On-chip Temperature Compensation