Phase-frequency detector (PFD) forms control signal for VCO tuning. PFD compares phases of divided VCO signal and divided reference oscillator signal and detects phase difference. Charge pump generates pulses for loop filter. The CP output stage is an amplifier equalizing a buffer reference voltage of CP output current adjustment with a loop filter voltage; and an amplifier minimizing the disbalance of the charging/discharge current in loop filter capacitors.
Reference frequency 24.84 MHz.
The block is fabricated on iHP SiGe BiCMOS 0.25 um (SGB25V) technology.
- iHP SGB25V
- Input signals with low amplitude
- Low disbalance of output current
- Minimum disbalance of the charging/discharge current in loop filter capacitors
- Supported foundries: TSMC, UMC, Global Foundries, SMIC, iHP, AMS, Vanguard, SilTerra
- Schematic or NetList
- Abstract model (.lef and .lib files)
- Layout view (optional)
- Behavioral model (Verilog)
- Extracted view (optional)
- DRC, LVS, antenna report
- Test bench with saved configurations (optional)
- Phase-locked loop synthesizer