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XPS Video and LCD Controller IP Core
The Video and LCD Controller IP Core interfaces to a PLB V4.6 bus for reading video data and for register access. The core can control both passive and active (TFT) LCD displays as well as provide video data and timing for VGA and DVI interfaced displays. The IP core is intended for Xilinx based embedded FPGA designs.
查看 PLB Bus Based Video Controller 详细介绍：
- 查看 PLB Bus Based Video Controller 完整数据手册
- 联系 PLB Bus Based Video Controller 供应商
Block Diagram of the PLB Bus Based Video Controller
