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Pipelined High Performance Configurable Microcontroller
The DP80390XP is an ultra high performance, speed optimized soft core of a single-chip 8-bit embedded controller, intended to operate with fast (typically on-chip) and slow (off-chip) memories. It supports up to 8 MB of linear code space and 16 MB of linear data space. The core has been designed with a special concern about performance to power consumption ratio. This ratio is extended by an advanced power management PMU unit.
The DP80390XP soft core is 100% binary-compatible with the industry standard 8051 8-bit microcontroller. There are two configurations of the DP80390XP: Harvard, where internal data and program buses are separated, and von Neumann, with common program and external data bus. The DP80390XP has a Pipelined RISC architecture and executes 85-200 million instructions per second. Dhrystone 2.1 benchmark program runs from 11.46 to 15.55 times faster, than the original 80C51 at the same frequency. The same C compiler was used for benchmarking of the core vs 80C51 with the same settings. This performance can also be exploited to great advantage in low power applications, where the core can be clocked over ten times more slower than the original implementation, without performance depletion.
The DP80390XP is delivered with fully automated testbench and complete set of tests, allowing easy package validation, at each stage of SoC design flow.
Each of the DCD's 80390 Core has built-in support for the DCD Hardware Debug System, called DoCD . It is a real-time hardware debugger, which provides debugging capability of a whole System on Chip (SoC).
Unlike other on-chip debuggers, the DoCD provides a non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller, including all registers, internal and external program memories and all SFRs, including user defined peripherals.
The DP80390XP soft core is 100% binary-compatible with the industry standard 8051 8-bit microcontroller. There are two configurations of the DP80390XP: Harvard, where internal data and program buses are separated, and von Neumann, with common program and external data bus. The DP80390XP has a Pipelined RISC architecture and executes 85-200 million instructions per second. Dhrystone 2.1 benchmark program runs from 11.46 to 15.55 times faster, than the original 80C51 at the same frequency. The same C compiler was used for benchmarking of the core vs 80C51 with the same settings. This performance can also be exploited to great advantage in low power applications, where the core can be clocked over ten times more slower than the original implementation, without performance depletion.
The DP80390XP is delivered with fully automated testbench and complete set of tests, allowing easy package validation, at each stage of SoC design flow.
Each of the DCD's 80390 Core has built-in support for the DCD Hardware Debug System, called DoCD . It is a real-time hardware debugger, which provides debugging capability of a whole System on Chip (SoC).
Unlike other on-chip debuggers, the DoCD provides a non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller, including all registers, internal and external program memories and all SFRs, including user defined peripherals.
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8051 IP
- Pipelined High Performance Microcontroller
- Super-Fast 8051 Microcontroller Core with Configurable Features and Peripherals
- High Performance 8051 Compatible CPU Core
- Instruction Set Compatible with the 8051 8-bit Microcontroller Architecture
- High Performance / Low Power Microcontroller Core
- Intel™ 8051 8-bit Microcontroller