Original Lossless codec IP core - Full HD 30fps@126MHz (1Sample/clk)
PHY IP for PCIe 6.0 on TSMC N5
The Synopsys PHY IP for PCIe 6.0 seamlessly interoperates with Synopsys Controller IP for PCIe 6.0 to provide a low-risk solution that designers can use to accelerate time-to-market and efficiently deliver differentiated products that require the 64GT/s PCIe 6.0 technology.
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Video Demo of the PHY IP for PCIe 6.0 on TSMC N5
This PCI-SIG DevCon 2022 video shows the industry’s first complete hardware demo of PCIe 6.0 with an end-to-end system from root complex to endpoint. The demo uses the Synopsys PCIe 6.0 Controller and PHY IP and shows successful link up and performance metrics.
PCIe IP
- PCIe 5.0 Integrity and Data Encryption Security Module
- PCIe 6.0 Integrity and Data Encryption Security Module
- PCIe 5.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC
- Multi-protocol SerDes PMA
- PCIe Gen 6 SERDES IP - supports up to 112G LR ethernet with low power and latency
- 56G Serdes in 7nm bundled with PCie Gen 5 controller IP