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PHY IP for HBM2 for Samsung 10LPP
Artificial intelligence (AI), high-performance computing (HPC), image processing, and autonomous driving applications generate and consume large volumes of data and require very high memory bandwidth. The Cadence® Denali® PHY IP for HBM2 for the Samsung 10LPP Process is an ideal solution for meeting these high-performance applications.
The PHY IP for HBM2 is comprised of architectural improvements drawn from previous-generation DDR5 and LPDDR4 PHYs, achieving breakthrough performance, low energy per bit, and low area relative to the bandwidth provided. The PHY IP for HBM2 was developed by experienced teams with industry-leading domain expertise and extensively validated with multiple hardware platforms. It is engineered to quickly and easily integrate into SoCs, and is verified with the Denali Controller IP for HBM2 as part of a complete memory subsystem solution.
The PHY IP for HBM2 is comprised of architectural improvements drawn from previous-generation DDR5 and LPDDR4 PHYs, achieving breakthrough performance, low energy per bit, and low area relative to the bandwidth provided. The PHY IP for HBM2 was developed by experienced teams with industry-leading domain expertise and extensively validated with multiple hardware platforms. It is engineered to quickly and easily integrate into SoCs, and is verified with the Denali Controller IP for HBM2 as part of a complete memory subsystem solution.
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Block Diagram of the PHY IP for HBM2 for Samsung 10LPP
HBM2 PHY IP
- Rambus HBM2/2E Memory PHY
- HBM2 PHY in TSMC (16nm)
- HBM2/2e PHY GF 12/14LPP from INNOSILICON
- HBM2/2e PHY TSMC 12FFC/16FFCLL from INNOSILICON
- HBM2/2e PHY From INNOSILICON - High Performancce, Low Power and Low Latency Design in a Small Area
- Unlimited licenses, HBM2E, HBM3, Hard PHY, Customized, Turnkey solution