MIPI C-PHY v1.2 D-PHY v2.1 RX 2 trios/2 Lanes in TSMC (16nm,N6, N5)
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PHY for PCIe 7.0 and CXL for TSMC N3E/N3P
Most advanced PHY and Controller for HPC, AI/ML, Data communications, networking, and storage systems
The Cadence® PHY IP for PCI Express® (PCIe®) 7.0 for TSMC delivers a data rate of up to 128GTps in PAM4 mode and 64/32/16/8/5/2.5GTps in NRZ mode. Designed specifically for infrastructure and data center applications, the PHY features advanced long-reach.
The Cadence® PHY IP for PCI Express® (PCIe®) 7.0 for TSMC delivers a data rate of up to 128GTps in PAM4 mode and 64/32/16/8/5/2.5GTps in NRZ mode. Designed specifically for infrastructure and data center applications, the PHY features advanced long-reach.
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PCIe IP
- PCIe 5.0 Integrity and Data Encryption Security Module
- PCIe 6.1 Controller
- PCIe 5.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC
- Multi-protocol SerDes PMA - PCIe1 PCIe2 PCIe3 PCIe4 PCIe5 and more
- PCIe Gen 6 SERDES IP - supports up to 112G LR ethernet with low power and latency
- 56G Serdes in 7nm bundled with PCie Gen 5 controller IP