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PHY for PCIe 6.0 and CXL for Samsung SF5A
Most advanced PHY and Controller for HPC, AI/ML, Data communications, networking, and storage systems
The Cadence® PHY IP for PCI Express® (PCIe®) 6.0 for Samsung SF5A delivers a data rate of up to 64GTps in PAM4 mode and 32/16/8/5/2.5GTps in NRZ mode. Designed specifically for infrastructure and data center applications, the PHY features advanced long-reach equalization and clock-data-recovery capabilities to achieve exceptional performance and reliability. Optimized for low latency and low active/standby power consumption, the PHY is ideal for deployment in time-critical and power-sensitive applications in high-performance computing (HPC), artificial intelligence / machine learning (AI/ML), data communications, networking, and storage systems. Cadence PHY IP is highly versatile and scalable. The PHY can be configured to support X1, X2, X4, X8, and X16 lane widths. The embedded bifurcation capability allows multiple PCIe links of various link widths to co-exist and operate independently in the same macro. A comprehensive set of diagnostic and test features is incorporated to enable faster silicon bring-up and simplify troubleshooting. EyeSurf graphic interface provides convenient access to real-time eye scope and bit-error-rate (BER) computations to monitor the link performance during live traffic. The PHY IP is fully compliant to PCIe 6.0, 5.0, 4.0, 3.1, 2.1, and 1.1 as well as Compute Express Link (CXL) 2.0, 1.1 specifications. It is engineered to quickly and easily integrate into any system-on-chip (SoC) design. Moreover, the PHY IP connects seamlessly to Cadence’s PCIe and CXL controllers. The integrated total solution from Cadence ensures faster time to market by reducing the development cycle and minimizing risks.
The Cadence® PHY IP for PCI Express® (PCIe®) 6.0 for Samsung SF5A delivers a data rate of up to 64GTps in PAM4 mode and 32/16/8/5/2.5GTps in NRZ mode. Designed specifically for infrastructure and data center applications, the PHY features advanced long-reach equalization and clock-data-recovery capabilities to achieve exceptional performance and reliability. Optimized for low latency and low active/standby power consumption, the PHY is ideal for deployment in time-critical and power-sensitive applications in high-performance computing (HPC), artificial intelligence / machine learning (AI/ML), data communications, networking, and storage systems. Cadence PHY IP is highly versatile and scalable. The PHY can be configured to support X1, X2, X4, X8, and X16 lane widths. The embedded bifurcation capability allows multiple PCIe links of various link widths to co-exist and operate independently in the same macro. A comprehensive set of diagnostic and test features is incorporated to enable faster silicon bring-up and simplify troubleshooting. EyeSurf graphic interface provides convenient access to real-time eye scope and bit-error-rate (BER) computations to monitor the link performance during live traffic. The PHY IP is fully compliant to PCIe 6.0, 5.0, 4.0, 3.1, 2.1, and 1.1 as well as Compute Express Link (CXL) 2.0, 1.1 specifications. It is engineered to quickly and easily integrate into any system-on-chip (SoC) design. Moreover, the PHY IP connects seamlessly to Cadence’s PCIe and CXL controllers. The integrated total solution from Cadence ensures faster time to market by reducing the development cycle and minimizing risks.
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PCIe 6.0 IP
- PCIe 6.0 Integrity and Data Encryption Security Module
- PCIe 6.0 PHY in TSMC (N6, N5, N4P, N3P, N3E)
- PCIe 6.0 PHY in Samsung (SF5A, SF4X, SF2)
- PCIe 6.1 Controller
- 1 to 64 Gbps PCI-Express (PCIe) 6.0 and CXL 3.0 PHY
- Configurable controllers for PCIe 6.0 supporting Endpoint, Root Complex, Switch Port, and Dual Mode applications