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PHY for PCIe 5.0 and CXL for TSMC 5nm FinFet
Cadence 32G NRZ multi-protocol PHY
The Cadence® 32/25Gbps Multi-Link and Multi-Protocol PHY IP for TSMC 5nm FinFET is a high-performance SerDes operating from 1.25Gbps to 32Gbps and specifically designed for infrastructure and data center applications. It features long-reach equalization capability at very low active and standby power. The SerDes offers very low latency for time-critical applications for enterprise-level data communications, networking, and storage systems. The PHY IP provides extensive flexibility to mix and match protocols within the same macro. The PHY IP is designed to run PCI Express® (PCIe®), Compute Express Link (CXL), 25G-KR, and 10G-KR. Multiple test features are embedded and easily accessible by the end user. A user-friendly graphical interface called EyeSurf provides convenient access to real-time and non-destructive eye scope and bathtubs for monitoring the bit error rate (BER) and the link performance during live traffic. The PHY IP quickly and easily integrates into any system on chip (SoC) and connects seamlessly to the Cadence controller for full flexibility. This minimizes time and risk of device development. It offers integrators the advanced capabilities, flexibilities, and support for advanced, high-performance designs.
The Cadence® 32/25Gbps Multi-Link and Multi-Protocol PHY IP for TSMC 5nm FinFET is a high-performance SerDes operating from 1.25Gbps to 32Gbps and specifically designed for infrastructure and data center applications. It features long-reach equalization capability at very low active and standby power. The SerDes offers very low latency for time-critical applications for enterprise-level data communications, networking, and storage systems. The PHY IP provides extensive flexibility to mix and match protocols within the same macro. The PHY IP is designed to run PCI Express® (PCIe®), Compute Express Link (CXL), 25G-KR, and 10G-KR. Multiple test features are embedded and easily accessible by the end user. A user-friendly graphical interface called EyeSurf provides convenient access to real-time and non-destructive eye scope and bathtubs for monitoring the bit error rate (BER) and the link performance during live traffic. The PHY IP quickly and easily integrates into any system on chip (SoC) and connects seamlessly to the Cadence controller for full flexibility. This minimizes time and risk of device development. It offers integrators the advanced capabilities, flexibilities, and support for advanced, high-performance designs.
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PCIe 5.0 PHY IP
- PCIe 5.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC
- PCIe 5.0 PHY in TSMC (16nm, 12nm, N7, N6, N5, N4P, N3E, N3P)
- PCIe 5.0 Controller supporting Endpoint, Root Port, Switch, Bridge and advanced features
- PCIe 5.0 Controller with AMBA AXI interface
- PCIe 5.0 Customizable Embedded Multi-port Switch
- PCIe 5.0 PHY IP for Storage and High-Bandwidth Connection