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Phase-locked loop clock generator
It is a integer-N phase-locked loop frequency synthesizer (PLL) based on fully integrated 2GHz LC-VCO with low gain and fine phase noise performance. It work with reference frequency from 25 MHz XTAL oscillator or external signal source with frequency up to 500 MHz. Phase-frequency divider compare frequency can be equal or 2,3,4...63 times lower than reference. VCO frequency N-divider has programmable coefficient of division with step 1 in range 4 to 2047. Phase-frequency detector has built-in analog and digital lock detector circuits. Charge pump scheme with ADC and adjustable output current allow compensation VCO gain variation within band and keep loop gain constant. Integrated low-pass loop filter has adjustable values of resistance and capacitance for tune loop and get best phase-noise performance. All of output clocks have 0.5 duty cycle value using duty cycle recovery circuit.
The QF is designed using TSMC 65nm CRN65LP technology.
The QF is designed using TSMC 65nm CRN65LP technology.
特色
- TSMC CMOS 65 nm
- Low phase noise
- Fully integrated 2 GHz VCO
- Fully integrated loop filter with ability to use external loop filter.
- Built-in lock detection circuit
- High reference frequency spur rejection
- Adjustable value of charge pump output current
- Built-in ADC for measuring VCO control voltage value
- Digital loop gain compensation
- Low current consumption
- Adjustable power supply voltage
- Supported foundries: TSMC, UMC, Global Foundries, SMIC
可交付内容
- Schematic or NetList
- Abstract model (.lef and .lib files)
- Layout view (optional)
- Behavioral model (Verilog)
- Extracted view (optional)
- GDSII
- DRC, LVS, antenna report
- Test bench with saved configurations (optional)
- Documentation
应用
- Low jitter clock generation
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