Phase-locked loop clock generator
The QF is designed using TSMC 65nm CRN65LP technology.
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PLL in TSMC 65nm IP
- Deskew Frequency Synthesizer PLL
- Low Jitter PLL with Accurately Spaced 16-Phase Output Clocks
- Fractional-N Frequency Synthesizer PLL
- Integer-N Frequency Synthesizer PLL
- USB 2.0 PHY TSMC 5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm, 65nm, 130nm, 180nm
- Fractional-N PLL for Performance Computing in TSMC N6/N7