The phase-frequency detector (PFD) consists of 2 D-trigger with reset from external circuit, performed in ECL logic and multiplexer, which allow to switch the input signals to the corresponding inputs.
The block is fabricated on AMS BiCMOS 0.35 um technology.
- AMS BiCMOS 0.35 um
- Differential structure
- Ability to work with VCOs with both positive and negative frequency dependence of the control voltage
- Input frequencies up to 100MHz
- Only-up/only-down test modes
- External reset circuit
- Supported foundries: TSMC, UMC, Global Foundries, SMIC, iHP, AMS, Vanguard, SilTerra, .
- Schematic or NetList
- Abstract model (.lef and .lib files)
- Layout view (optional)
- Behavioral model (Verilog)
- Extracted view (optional)
- DRC, LVS, antenna report
- Test bench with saved configurations (optional)
- Phase-locked loop synthesizer