28G LR Multi-Protocol SerDes (MPS) PHY - GLOBALFOUNDRIES 12nm
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Phase-frequency detector in ECL logic
The phase-frequency detector (PFD) consists of 2 D-trigger with reset from external circuit, performed in ECL logic and multiplexer, which allow to switch the input signals to the corresponding inputs.
The block is fabricated on AMS BiCMOS 0.35 um technology.
The block is fabricated on AMS BiCMOS 0.35 um technology.
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Phase-frequency detector IP
- 24.84 MHz Phase-frequency detector with charge pump (input amplitude 150…210 mV)
- 0.1 to 25 MHz Phase-frequency detector with charge pump
- 24.84 MHz Phase-frequency detector with charge pump
- 0.32 to 10 MHz Phase-frequency detector
- PLL CMOS phase-frequency detector with ECL charge pump
- PLL ECL phase-frequency detector with ECL charge pump