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Performance-efficient, ultra-low power, compact ARC SEM security processors help protect against logical, hardware, physical and side-channel attacks
The Synopsys ARC® SEM Family of performance-efficient, ultra-low power, compact security processors enables designers to integrate security into their SoC to protect against logical, hardware and physical attacks.
The ARC SEM security processors are RISC cores based on the ARCv2 instruction set architecture (ISA), with the capability to closely couple memories and peripherals. ARC SEM processors include SecureShield® technology to enable creation of a Trusted Execution Environment (TEE) to isolate multiple execution contexts and protect secure functions from software vulnerabilities in user code.
The ARC SEM processors include protection from side-channel attacks, which rely on information from the physical implementation rather than exploiting a direct weakness in the security measures themselves. They can be implemented as either a standalone secure core or a single core performing both secure and normal functions.
The ASIL D compliant ARC SEM130FS Safety and Security Processor adds hardware redundancy to its side-channel-attack protected processor to mitigate random hardware faults and avoid system failures for ADAS, telematics, radar, V2X communications, and industrial SoCs.
The ARC SEM security processors are RISC cores based on the ARCv2 instruction set architecture (ISA), with the capability to closely couple memories and peripherals. ARC SEM processors include SecureShield® technology to enable creation of a Trusted Execution Environment (TEE) to isolate multiple execution contexts and protect secure functions from software vulnerabilities in user code.
The ARC SEM processors include protection from side-channel attacks, which rely on information from the physical implementation rather than exploiting a direct weakness in the security measures themselves. They can be implemented as either a standalone secure core or a single core performing both secure and normal functions.
The ASIL D compliant ARC SEM130FS Safety and Security Processor adds hardware redundancy to its side-channel-attack protected processor to mitigate random hardware faults and avoid system failures for ADAS, telematics, radar, V2X communications, and industrial SoCs.
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