MIPI D-PHY Rx-Only 2 Lanes in TSMC (40nm, 28nm, 22nm, 16nm, 12nm, N7, N6)
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PCIe3 SSCG PLL - GLOBALFOUNDRIES 12LP+
Analog Bits’ PCIe Gen3 SSCG PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Express Gen3 serial bus standard where SRIS (Separate RefClk Independent Spread-Spectrum clock generation) is required. This SSCG PLL is designed for digital logic processes and use robust design techniques to work in noisy SoC environments.
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