UniPHY™ IoT IP: Ultra Low Power and Smallest PHY area for low cost Chiplets
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PCIe refclk buffer on 14nm
The output buffer to deliver a differential clock signal from inside chip to outside for PCIe interface
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Block Diagram of the PCIe refclk buffer on 14nm
PCIe IP
- PCIe 5.0 Integrity and Data Encryption Security Module
- PCIe 6.0 Integrity and Data Encryption Security Module
- PCIe 5.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC
- Multi-protocol SerDes PMA - PCIe1 PCIe2 PCIe3 PCIe4 PCIe5 and more
- PCIe Gen 6 SERDES IP - supports up to 112G LR ethernet with low power and latency
- 56G Serdes in 7nm bundled with PCie Gen 5 controller IP