You are here:
PCIe refclk buffer (14nm)
The output buffer to deliver a differential clock signal from inside chip to outside for PCIe interface
查看 PCIe refclk buffer (14nm) 详细介绍：
- 查看 PCIe refclk buffer (14nm) 完整数据手册
- 联系 PCIe refclk buffer (14nm) 供应商
Block Diagram of the PCIe refclk buffer (14nm)
PCIe IP
- PCIe 5.0 Integrity and Data Encryption Security Module
- PCIe 6.1 Controller
- PCIe 5.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC
- Multi-protocol SerDes PMA - PCIe1 PCIe2 PCIe3 PCIe4 PCIe5 and more
- PCIe Gen 6 SERDES IP - supports up to 112G LR ethernet with low power and latency
- 56G Serdes in 7nm bundled with PCie Gen 5 controller IP