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PCIe Multifunction IP Core for Xilinx 7 FPGAs
The PCI Express Specification allows Endpoints that incorporate more than one physical PCIe-Function. Such Endpoints are called Multi-Function Devices. The big advantage of a Multi-Function Device is, that a separate device driver can be associated to each physical Function. This simplifies driver development and maintenance significantly by separating different peripheral Functions logically into different device drivers.
The Xilinx PCIe Hardblocks in the 7 Series device family however do not support more than one physical PCIe Function and do not support Multi-Function Devices natively.
Smartlogic’s new patented Multi-Function Extension IP-Core removes this restriction by extending the Xilinx PCIe Hardblock with up to 6 physical PCIe Functions. Compared to a PCIe Soft IP-Core solution with Multi-Function support, the Smartlogic IP-Core uses only a fraction of logic resources and will fit even in the smallest Artix FPGA Devices.
The Xilinx PCIe Hardblocks in the 7 Series device family however do not support more than one physical PCIe Function and do not support Multi-Function Devices natively.
Smartlogic’s new patented Multi-Function Extension IP-Core removes this restriction by extending the Xilinx PCIe Hardblock with up to 6 physical PCIe Functions. Compared to a PCIe Soft IP-Core solution with Multi-Function support, the Smartlogic IP-Core uses only a fraction of logic resources and will fit even in the smallest Artix FPGA Devices.
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Block Diagram of the PCIe Multifunction IP Core for Xilinx 7 FPGAs
PCIe IP
- PCIe 5.0 Integrity and Data Encryption Security Module
- PCIe 6.0 Integrity and Data Encryption Security Module
- PCIe 5.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC
- Multi-protocol SerDes PMA
- PCIe Gen 6 SERDES IP - supports up to 112G LR ethernet with low power and latency
- 56G Serdes in 7nm bundled with PCie Gen 5 controller IP