PCI Express PHY serial link PIPE Transceiver IP cell/hard macro
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PCIe Multifunction IP Core for Intel FPGAs
The PCI Express specification allows endpoints
that incorporate more than one physical PCIe
function. Such endpoints are called
multifunction devices. The big advantage of a
multifunction device is, that a separate device
driver can be associated to each physical
function. This simplifies driver development and
maintenance significantly by separating the
peripheral functions logically into different
device drivers.
The Intel PCIe hardblocks in the Cyclone V /
Arria V FPGA device families support multifunction devices natively but on a very low
level.
Smartlogic’s PCI Express multifunction IP core
for Cyclone V FPGAs offers a fully productized
IP core with optional DMA support. The core
operates with industry standard interfaces (AXI
and AXI Stream) and encapsulates the whole
PCI Express protocol know-how. This frees the
FPGA designer to concentrate on the project
specific design tasks.
that incorporate more than one physical PCIe
function. Such endpoints are called
multifunction devices. The big advantage of a
multifunction device is, that a separate device
driver can be associated to each physical
function. This simplifies driver development and
maintenance significantly by separating the
peripheral functions logically into different
device drivers.
The Intel PCIe hardblocks in the Cyclone V /
Arria V FPGA device families support multifunction devices natively but on a very low
level.
Smartlogic’s PCI Express multifunction IP core
for Cyclone V FPGAs offers a fully productized
IP core with optional DMA support. The core
operates with industry standard interfaces (AXI
and AXI Stream) and encapsulates the whole
PCI Express protocol know-how. This frees the
FPGA designer to concentrate on the project
specific design tasks.
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Block Diagram of the PCIe Multifunction IP Core for Intel FPGAs
