Analog Front End: 8x 12-bit 2 GSPSADCs, 4x 12-bit 200 MSPS ADCs, TVM, PLL, LDO
PCIe Gen3 to SRIO Gen3 Bridge (FPGA)
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Block Diagram of the PCIe Gen3 to SRIO Gen3 Bridge (FPGA)

PCIe IP
- PCIe 5.0 Integrity and Data Encryption Security Module
- PCIe 6.1 Controller
- PCIe 5.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC
- Multi-protocol SerDes PMA - PCIe1 PCIe2 PCIe3 PCIe4 PCIe5 and more
- PCIe Gen 6 SERDES IP - supports up to 112G LR ethernet with low power and latency
- 56G Serdes in 7nm bundled with PCie Gen 5 controller IP