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PCIe Gen3 PHY - TSMC 28nm HPC/HPC+
* Endpoint or Root Complex
* PCIe standard multi-lane interface
* PCIe power savings modes
* Port bifurcation support
* PCIe standard multi-lane interface
* PCIe power savings modes
* Port bifurcation support
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Block Diagram of the PCIe Gen3 PHY
SerDes IP
- PCIe 5.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC
- Low-Latency SerDes PMA
- Multi-protocol SerDes PMA
- 1-56/112G Multi-protocol Serdes (Interlaken, JESD204, CPRI, Ethernet, OIF/CEI)
- 400G ultra low latency 56/112G FEC and SERDES IP sub 10ns latency
- PCIe Gen 6 SERDES IP - supports up to 112G LR ethernet with low power and latency