PCIe Gen2 PHY

The PCIe2 PHY is a complete mixed-signal semiconductor intellectual property (IP) solution, designed for single-chip integration into PCI Express applications. The PCIe 2 PHY pcie2_pipe_PxL_xN includes all the necessary logical, geometric, and physical design files to implement complete PCI Express 2.0 physical layer capability for 5-Gbps operation, connecting a root complex, switch, or endpoint to a PCI Express system. The PCIe 2 PHY supports the 5-Gbps data rate of the PCI Express Gen 2 specification and is backward compatible with the 2.5-Gbps Gen 1.1 specification with only inferred idle detection supported.

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