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PCIe Gen1/2 PHY
Atria Logic Pvt. Ltd. provides the complete design services for PCI Express. (2.5GT/s, 5GT/s) Our expertise overs the breadth of PCI-SIG’s 3.0 specification of PCIe. We have a highly skilled team of experts who can deliver the services on PCIe physical layer including
MAC
PCS
PIPE interface (8 bit, 16 bit and 32 bit interface)
Scrambler
The PHY layer is essentially the PIPE (Physical Interface for PCIe Express). The designed PIPE interface follows the INTEL’s PIPE spec. This Intel's spec is being used by other vendors like Xilinx, Altera and PLDA with slight modifications in LTSSM and power management states. However the basic Interface mentioned in Intel's spec is maintained by all vendors and so our design.
The main goal of Physical Layer is to establish the physical connection or channel for proper communication of transactions coming from above layer (Transaction Layer and Data Link Layer).
The main functions of Tx side of PHY layer are listed below
Link training through ordered sets TS1 & TS2
Insertion of SKP ordered sets every 1538 symbols for elastic buffer overflow/underflow management.
Sending Logical Idles in particular state of LTSSM and whenever there is no data available to send.
Sending ElOS (Electrical Idle) as dictated by ASPM and Software Power management.
Sending FTS(Fast Training Sequence) ordered sets whiling coming back to active state from Low power state.
Generation of PIPE signals which includes
Tx_data[32 or 16 bit]
D/K [4 or 2bit]
Tx_Elec_Idle
Tx_Compliance
Rate[1:0]
Width [1:0]
Pwr_dwn[2:0]
Reset_PhY
TxdetectRx
Insertion of STP, SDP, END kontrol characters (Implemented in DLL)
All the Data packets except Kontrol characters and ordered sets will pass through scrambler.
MAC
PCS
PIPE interface (8 bit, 16 bit and 32 bit interface)
Scrambler
The PHY layer is essentially the PIPE (Physical Interface for PCIe Express). The designed PIPE interface follows the INTEL’s PIPE spec. This Intel's spec is being used by other vendors like Xilinx, Altera and PLDA with slight modifications in LTSSM and power management states. However the basic Interface mentioned in Intel's spec is maintained by all vendors and so our design.
The main goal of Physical Layer is to establish the physical connection or channel for proper communication of transactions coming from above layer (Transaction Layer and Data Link Layer).
The main functions of Tx side of PHY layer are listed below
Link training through ordered sets TS1 & TS2
Insertion of SKP ordered sets every 1538 symbols for elastic buffer overflow/underflow management.
Sending Logical Idles in particular state of LTSSM and whenever there is no data available to send.
Sending ElOS (Electrical Idle) as dictated by ASPM and Software Power management.
Sending FTS(Fast Training Sequence) ordered sets whiling coming back to active state from Low power state.
Generation of PIPE signals which includes
Tx_data[32 or 16 bit]
D/K [4 or 2bit]
Tx_Elec_Idle
Tx_Compliance
Rate[1:0]
Width [1:0]
Pwr_dwn[2:0]
Reset_PhY
TxdetectRx
Insertion of STP, SDP, END kontrol characters (Implemented in DLL)
All the Data packets except Kontrol characters and ordered sets will pass through scrambler.
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Block Diagram of the PCIe Gen1/2 PHY
PCIe IP
- PCIe 5.0 Integrity and Data Encryption Security Module
- PCIe 6.0 Integrity and Data Encryption Security Module
- PCIe 5.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC
- Multi-protocol SerDes PMA
- PCIe Gen 6 SERDES IP - supports up to 112G LR ethernet with low power and latency
- 56G Serdes in 7nm bundled with PCie Gen 5 controller IP