You are here:
PCIE Gen.II PHY; UMC 65nm LP/RVT LowK Logic Process.
PCIE Gen.II PHY; UMC 65nm LP/RVT LowK Logic Process.
查看 PCIE Gen.II PHY; UMC 65nm LP/RVT LowK Logic Process. 详细介绍：
- 查看 PCIE Gen.II PHY; UMC 65nm LP/RVT LowK Logic Process. 完整数据手册
- 联系 PCIE Gen.II PHY; UMC 65nm LP/RVT LowK Logic Process. 供应商
Interface Solution IP
- Compute Express Link (CXL) 2.0 Controller with AMBA AXI interface
- PCIe 6.1 Controller
- PCIe 5.0 Controller with AMBA AXI interface
- PCIe 4.0 Controller with AMBA AXI interface
- Very compact (500 LUTs) Camera Sensor Receiver Interface Converting from MIPI CSI-2 to AXI4-Stream Video Standard
- HW/SW interface foundation for design innovation