PCIe Gen 4.0 PHY - FlipChip - TSMC 16FF

The Cadence PHY IP for PCIe Gen4 is a hard PHY macro consisting of a Physical Media Attachment (PMA) layer and a soft Physical Coding Sublayer (PCS). It is designed to the PCIe® 4.0 specification, and operates at 16.0GTps, 8.0GTps, 5.0GTps, and 2.5GTps. The PCS complies with the PIPE 4.2 specification, and provides support for the dynamic equalization features of PCIe Gen4. The Cadence PHY IP for PCIe Gen4 is architected to quickly and easily integrate into any system on chip (SoC), and to connect seamlessly to a Cadence, or third party, PIPE 3.0- or PIPE 4.0-compliant controller.

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