28G LR Multi-Protocol SerDes (MPS) PHY - GLOBALFOUNDRIES 12nm
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PCIe Controller for USB4 Hosts and Devices, supporting PCIe Tunneling
Rambus PCIe Controller IP for USB4 is a configurable and scalable PCI Express controller soft IP designed for ASIC and FPGA implementations. It supports the PCI Express 5.0 specification, and implements the required features mandated by the USB4 Specification. The IP can be configured to support endpoint, root port, switch port, and dual-mode topologies, allowing for a variety of use models. The provided Graphical User Interface (GUI) Wizard allows designers to tailor the IP to their exact requirements, by enabling, disabling, and adjusting a vast array of parameters. Rambus PCIe Controller IP for USB4 enables designers to support tunneling of PCIe in USB4 Devices or Hosts for attaching PCIe devices either internally or externally. By implementing internal PCIe devices in their USB4 designs, designers can differentiate their USB4 ICs while reducing latency and power consumption.
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Block Diagram of the PCIe Controller for USB4 Hosts and Devices, supporting PCIe Tunneling
PCIe IP
- PCIe 5.0 Integrity and Data Encryption Security Module
- PCIe 6.0 Integrity and Data Encryption Security Module
- PCIe 5.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC
- Multi-protocol SerDes PMA
- PCIe Gen 6 SERDES IP - supports up to 112G LR ethernet with low power and latency
- 56G Serdes in 7nm bundled with PCie Gen 5 controller IP