MIPI D-PHY Tx-Only 2 Lanes in TSMC (28nm, 22nm, 16nm, 12nm, N7, N6)
PCIe 7.0 PHY for TSMC N5
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PCIe 7.0 PHY IP
- PCIe 7.0 PHY IP supporting the latest features of the evolving PCIe 7.0 specification to enable 128 GT/s and up to x16 lane configurations
- PCIe 7.0 PHY in TSMC (N5, N3P)
- PCIe 7.0 Controller
- PCIe 7.0 Controller with AXI
- PCIe 7.0 Controller (can be configured to support EP, RP, DM, or SW applications)